Parasitic resistance reduction in deep submicron dual-gate transistors with partially elevated source/drain extension regions fabricated by complementary metal-oxide-semiconductor technologies

被引：11

作者：

Sugihara, K ^{[1
]}

Miura, N ^{[1
]}

Furukawa, T ^{[1
]}

Nakahata, T ^{[1
]}

Nishioka, Y ^{[1
]}

Yamakawa, S ^{[1
]}

Abe, Y ^{[1
]}

Maruno, S ^{[1
]}

Tokuda, Y ^{[1
]}

机构：

[1] Mitsubishi Elect Co, Adv Technol R&D Ctr, Itami, Hyogo 6648641, Japan

来源：

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS | 2000年 / 39卷 / 2A期

关键词：

CMOS; MOSFET; ULSI; parasitic resistance; elevated source/drain; epitaxial growth; UHV-CVD;

D O I：

10.1143/JJAP.39.387

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

Deep submicron dual-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) with partially elevated source/drain (S/D) structures were fabricated using complementary MOS (CMOS) technologies. In comparison with well-defined conventional MOSFETs, it is revealed that the drivability is appreciably enhanced by the S/D elevation and, further, that a p-channel MOSFET gains more from the SID elevation than an n-channel MOSFET. Investigation of the parasitic resistance is consistent with the results of the transistor characteristics.

引用

页码：387 / 389

页数：3

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