Test Compaction Under Bounded Transparent-Scan

被引:0
作者
Pomeranz, Irith [1 ]
机构
[1] Purdue Univ, Sch Elect & Comp Engn, W Lafayette, IN 47907 USA
来源
2019 IEEE 37TH VLSI TEST SYMPOSIUM (VTS) | 2019年
关键词
TEST-GENERATION; CIRCUITS;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper studies the concept of bounded transparent-scan to take advantage of the test compaction capabilities of transparent-scan at the significantly lower computational cost of conventional multicycle tests. Transparent-scan considers the scan enable input of a standard-scan circuit as a regular primary input. This allows arbitrary sequences of scan shift and functional capture cycles to be used as part of a transparent-scan sequence, contributing to test compaction. However, it also has the computational cost of sequential fault simulation over all the clock cycles of the test application process. With bounded transparent-scan, tests start and end with scan- in and scan- out operations that do not need to be simulated. Between the scan operations, arbitrary sequences of scan shift and functional capture cycles are allowed to support test compaction. The paper develops a test compaction procedure under bounded transparent-scan, and presents experimental results for benchmark circuits to demonstrate its effectiveness.
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页数:6
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