A low latency semi-systolic multiplier over GF(2m)

被引：5
|
作者：
Kim, Kee-Won [1 ]
Kim, Seung-Hoon [2 ]
机构：
[1] Dankook Univ, Coll Engn, Cheonan 330714, South Korea
[2] Dankook Univ, Dept Multimedia Engn, Cheonan 330714, South Korea
来源：
IEICE ELECTRONICS EXPRESS | 2013年 / 10卷 / 13期
关键词：
cryptography; finite field arithmetic; modular multiplication; semi-systolic array; CONCURRENT ERROR-DETECTION; POLYNOMIAL BASIS MULTIPLIER;
D O I：
10.1587/elex.10.20130354
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A finite field multiplier is commonly used in implementations of cryptosystems and error correcting codes. In this paper, we present a low latency semi-systolic multiplier over GF(2(m)). We propose a finite field multiplication algorithm to reduce latency based on parallel computation. The proposed multiplier saves at least 31% time complexity as compared to the corresponding existing structures.
引用
收藏
页数：6
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