A low latency semi-systolic multiplier over GF(2m)

被引:5
|
作者
Kim, Kee-Won [1 ]
Kim, Seung-Hoon [2 ]
机构
[1] Dankook Univ, Coll Engn, Cheonan 330714, South Korea
[2] Dankook Univ, Dept Multimedia Engn, Cheonan 330714, South Korea
来源
IEICE ELECTRONICS EXPRESS | 2013年 / 10卷 / 13期
关键词
cryptography; finite field arithmetic; modular multiplication; semi-systolic array; CONCURRENT ERROR-DETECTION; POLYNOMIAL BASIS MULTIPLIER;
D O I
10.1587/elex.10.20130354
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A finite field multiplier is commonly used in implementations of cryptosystems and error correcting codes. In this paper, we present a low latency semi-systolic multiplier over GF(2(m)). We propose a finite field multiplication algorithm to reduce latency based on parallel computation. The proposed multiplier saves at least 31% time complexity as compared to the corresponding existing structures.
引用
收藏
页数:6
相关论文
共 50 条
  • [21] Super Digit-Serial Systolic Multiplier Over GF(2m)
    Lee, Chiou-Yng
    2012 SIXTH INTERNATIONAL CONFERENCE ON GENETIC AND EVOLUTIONARY COMPUTING (ICGEC), 2012, : 509 - 513
  • [22] A NEW BIT-SERIAL SYSTOLIC MULTIPLIER OVER GF(2M)
    ZHOU, BB
    IEEE TRANSACTIONS ON COMPUTERS, 1988, 37 (06) : 749 - 751
  • [23] Efficient Bit-Parallel Systolic Multiplier over GF (2m)
    Mozhi, S. Arul
    Ramya, P.
    2016 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, AND OPTIMIZATION TECHNIQUES (ICEEOT), 2016, : 4899 - 4902
  • [24] Efficient Bit-Parallel Systolic Multiplier over GF (2m)
    Mozhi, S. Arul
    Ramya, P.
    2016 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, AND OPTIMIZATION TECHNIQUES (ICEEOT), 2016, : 4800 - 4803
  • [25] A systolic bit-parallel multiplier with flexible latency and complexity over GF(2m) using polynomial basis
    Zhang, Jingxian
    Song, Zheng
    Hu, Qingsheng
    ADVANCED MATERIALS AND ENGINEERING MATERIALS, PTS 1 AND 2, 2012, 457-458 : 848 - 855
  • [26] Low-complexity systolic multiplier over GF(2m) using weakly dual basis
    Lee, CY
    Lu, YC
    Lu, EH
    APCCAS 2002: ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1, PROCEEDINGS, 2002, : 367 - 372
  • [27] Pipelined systolic multiplier for finite fields GF(2m)
    Kim, HS
    Yoo, KY
    Kim, JJ
    Kim, TG
    INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED PROCESSING TECHNIQUES AND APPLICATIONS, VOLS I-V, PROCEEDINGS, 1999, : 1224 - 1229
  • [28] Efficient systolic modular multiplier/squarer for fast exponentiation over GF(2m)
    Choi, Se-Hyu
    Lee, Keon-Jik
    IEICE ELECTRONICS EXPRESS, 2015, 12 (11):
  • [29] An efficient Systolic multiplier for finite fields GF(2m)
    Kim, CH
    Han, SD
    Hong, CP
    PDPTA'2001: PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED PROCESSING TECHNIQUES AND APPLICATIONS, 2001, : 1366 - 1371
  • [30] Low complexity bit-parallel systolic multiplier over GF(2m) using irreducible trinomials
    Lee, CY
    IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 2003, 150 (01): : 39 - 42