A complete strategy for testing an on-chip multiprocessor architecture

被引：28

作者：

Aktouf, C ^{[1
]}

机构：

[1] Inst Natl Polytech Grenoble, F-38031 Grenoble, France

来源：

IEEE DESIGN & TEST OF COMPUTERS | 2002年 / 19卷 / 01期

关键词：

Algorithms - Integrated circuit testing - Random access storage - Routers - VLSI circuits;

D O I：

10.1109/54.980050

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

By dividing testing into three phases-router, RAM block, and processors-this strategy ensures an efficient tradeoff of test quality and cost.

引用

页码：18 / 28

页数：11

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