A complete strategy for testing an on-chip multiprocessor architecture

被引：28
作者：
Aktouf, C [1 ]
机构：
[1] Inst Natl Polytech Grenoble, F-38031 Grenoble, France
来源：
IEEE DESIGN & TEST OF COMPUTERS | 2002年 / 19卷 / 01期
关键词：
Algorithms - Integrated circuit testing - Random access storage - Routers - VLSI circuits;
D O I：
10.1109/54.980050
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
By dividing testing into three phases-router, RAM block, and processors-this strategy ensures an efficient tradeoff of test quality and cost.
引用
收藏
页码：18 / 28
页数：11
相关论文
共 7 条
  • [1] An implementation approach of the IEEE 1149.1 for the routing test of a VLSI massively parallel architecture
    Aktouf, C
    Robach, C
    Marinescu, A
    Mazare, G
    [J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1998, 12 (03): : 171 - 185
  • [2] Aktouf C., 1993, Proceedings. The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (Cat. No.93TH0571-0), P72, DOI 10.1109/DFTVS.1993.595645
  • [3] AKTOUF C, 1993, P IEEE EUR S LOS AL, P245
  • [4] A BUILT-IN SELF-TEST ALGORITHM FOR ROW COLUMN PATTERN SENSITIVE FAULTS IN RAMS
    FRANKLIN, M
    SALUJA, KK
    KINOSHITA, K
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25 (02) : 514 - 524
  • [5] Kogge P. M., 1994, Proceedings of the 1994 International Conference on Parallel Processing, P77
  • [6] Maunder C. M., 1991, Journal of Electronic Testing: Theory and Applications, V2, P27, DOI 10.1007/BF00134942
  • [7] ON CONNECTION ASSIGNMENT PROBLEM OF DIAGNOSABLE SYSTEMS
    PREPARATA, FP
    METZE, G
    CHIEN, RT
    [J]. IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS, 1967, EC16 (06): : 848 - +
1