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Selective Clock Gating Based on Comprehensive Power Saving Analysis
被引:0
作者
:
Park, Sora
论文数:
0
引用数:
0
h-index:
0
机构:
Seoul Natl Univ, Sch Elect & Comp Engn, Seoul, South Korea
Seoul Natl Univ, Sch Elect & Comp Engn, Seoul, South Korea
Park, Sora
[
1
]
Kim, Taewhan
论文数:
0
引用数:
0
h-index:
0
机构:
Seoul Natl Univ, Sch Elect & Comp Engn, Seoul, South Korea
Seoul Natl Univ, Sch Elect & Comp Engn, Seoul, South Korea
Kim, Taewhan
[
1
]
机构
:
[1]
Seoul Natl Univ, Sch Elect & Comp Engn, Seoul, South Korea
来源
:
2022 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 22)
|
2022年
基金
:
新加坡国家研究基金会;
关键词
:
D O I
:
10.1109/ISCAS48785.2022.9937589
中图分类号
:
TM [电工技术];
TN [电子技术、通信技术];
学科分类号
:
0808 ;
0809 ;
摘要
:
引用
收藏
页码:230 / 231
页数:2
相关论文
共 5 条
[1]
Albrecht C., 2005, IWLS 2005 Benchmarks
[2]
[Anonymous], DESIGN COMPILER USER
[3]
Hyun G., ICCAD 2019
[4]
NanGate, NANGATE 15NM OP CELL
[5]
Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating
论文数:
引用数:
h-index:
机构:
Wimer, Shmuel
Koren, Israel
论文数:
0
引用数:
0
h-index:
0
机构:
Univ Massachusetts, Dept Elect & Comp Engn, Amherst, MA 01003 USA
Technion Israel Inst Technol, Fac Elect Engn, IL-32000 Haifa, Israel
Koren, Israel
[J].
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,
2014,
22
(04)
: 771
-
778
←
1
→
共 5 条
[1]
Albrecht C., 2005, IWLS 2005 Benchmarks
[2]
[Anonymous], DESIGN COMPILER USER
[3]
Hyun G., ICCAD 2019
[4]
NanGate, NANGATE 15NM OP CELL
[5]
Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating
论文数:
引用数:
h-index:
机构:
Wimer, Shmuel
Koren, Israel
论文数:
0
引用数:
0
h-index:
0
机构:
Univ Massachusetts, Dept Elect & Comp Engn, Amherst, MA 01003 USA
Technion Israel Inst Technol, Fac Elect Engn, IL-32000 Haifa, Israel
Koren, Israel
[J].
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,
2014,
22
(04)
: 771
-
778
←
1
→