High-speed domino logic design

被引：0

作者：

Sahari, S. K. ^{[1
]}

Tiong, Colina P. ^{[1
]}

Rajaee, N. ^{[1
]}

Sapawi, R. ^{[1
]}

机构：

[1] Univ Malaysia Sarawak, Fac Engn, Dept Elect & Comp, Sarawak 94300, Malaysia

来源：

APACE: 2005 ASIA-PACIFIC CONFERENCE ON APPLIED ELECTROMAGNETICS, PROCEEDINGS | 2005年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Optimized standard CMOS-domino logic to a low cost logic and high speed design is presented. Ibis paper combines a footless dynamic circuit with a robust self-timed inverted clocking scheme, a serial transistor is removed and capacitances at the output node are reduced in the new structures. This can be highly upgrade the operation speed of the circuit with very low power dissipation. Parametric simulation in Microwind 2 shows that over 20% performances enhancement is achieved. However, there are always the tradeoffs in designing high speed CMOS circuit and certain design issues need to be catered. CMOS-domino logic has been believed to gain its popularity in application of desktop computer and mobile devices in near future.

引用

页码：280 / 283

页数：4

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