A processor allocation of DSP applications onto heterogeneous multiprocessor architectures

In recent years a great deal of research has been conducted in the area of scheduling of DSP data flow graphs (DFG) onto multiprocessing systems. In this paper, a new processor allocation technique is proposed. Both heterogeneous and general-purpose functional units are used during the resource allocation process. The proposed technique provides the designer with more flexibility to explore the design space by using different types of processing modules for the same task. The proposed allocation technique leads to different multiprocessor architectures for a given rate-optimal schedule of a DSP data flow graph. A satisfactory function is used to infer the quality of the obtained architectures in terms of the area and utilization of each of them. The proposed algorithm is applied to a well-known benchmark problem of DSP filter. It is seen that moving from a fully-homogenous to a fully-heterogeneous multiprocessor architecture results in decreasing the area of the design. However, a hybrid multiprocessor architecture brings about a trade off between the area and the utilization.