Hardware Architecture for Advanced Image Processing

被引:0
作者
Grabowski, Kamil [1 ]
Napieralski, Andrzej [1 ]
机构
[1] Tech Univ Lodz, Dept Microelect & Comp Sci, PL-90924 Lodz, Poland
来源
2010 IEEE NUCLEAR SCIENCE SYMPOSIUM CONFERENCE RECORD (NSS/MIC) | 2010年
关键词
image analysis; multicore processing; biometrics; iris recognition; biomedical image processing; IRIS RECOGNITION;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The computation speed offered by nowadays embedded systems allows combining advanced signal processing and data acquisition in dedicated architectures optimized for given applications. Such architectures can be used for 2D/3D signal analysis and reconstruction in such broad areas as: medical signal processing - tomography object reconstruction (USG, PET, CT, OCT, etc.), biomedical image analysis - automated object segmentation and diagnostic support, biometry - pattern recognition, etc. The technological advances in the scale of integration of integrated circuits as well as image acquisition and processing systems have played a major part in this trend. In particular, for medical image analysis common problems are content segmentation, analysis of selected objects, pattern estimation and storage. In the paper general architecture for advanced image processing is presented which can be adapted to specific needs, depending on intended use. This article describes a system for analysis of biometric data developed as part of the work conducted by the authors on the complete biometric identification system. Thus, the article focuses mostly on the biometrical iris identification system (1:N), chosen as an example well suited to the validation of the developed system. Several issues concerning efficient data processing using Field Programmable Arrays and Digital Signal Processors are presented on the basis of the described architecture. Algorithms computed on a desktop computer were adapted to this specialized, hardware-oriented architecture composed of Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGA). Obtained results are presented and the developed system is compared with some commercially-available solutions for iris recognition.
引用
收藏
页码:3626 / 3633
页数:8
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