Parallel multiplication using fast sorting networks

被引:2
作者
Fiore, PD [1 ]
机构
[1] Lockheed Martin Co, Signal Proc Ctr Sanders, Nashua, NH 03061 USA
关键词
parallel multiplier; partial product reduction; Dadda's counter; 4 : 2 compressor; bitonic sorting network;
D O I
10.1109/12.773800
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
A recent paper describes the use of Svoboda's binary counter in the construction of fast parallel multipliers. The resulting approach was shown to he faster than the conventional Dadda multiplier when the wordlength N was small. Unfortunately, the growth in the number of gates of that method was O(N-3) and the speed was O(N). In this paper, Batcher's bitonic sorting network and other efficient networks replace the Svoboda counter. The asymptotic growth rate in gates of these new methods is O(N-2 log(2) N), and the speed is O(log(2) N).
引用
收藏
页码:640 / 645
页数:6
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