共 8 条
[1]
Dadda L., 1965, ALTA FREQ, V34, P349
[2]
FAST MULTIPLIER BIT-PRODUCT MATRIX-REDUCTION USING BIT-ORDERING AND PARITY GENERATION
[J].
JOURNAL OF VLSI SIGNAL PROCESSING,
1994, 7 (03)
:249-257
[5]
VILLEGER D, 1993, P AS C SIGN SYST COM, V1, P781
[8]
[No title captured]