Implications of Cache Asymmetry on Server Consolidation Performance

被引:0
作者
Apparao, Padma [1 ]
Iyer, Ravi [1 ]
Newell, Don [1 ]
机构
[1] Intel Corp, Hardware Architecture Lab, Santa Clara, CA 95051 USA
来源
2008 IEEE INTERNATIONAL SYMPOSIUM ON WORKLOAD CHARACTERIZATION | 2008年
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Today's CMP platforms are designed to be symmetric in terms of platform resources such as shared caches. However, it is becoming increasingly important to understand the performance implications of asymmetric caches for two key reasons: (a) multi-workload scenarios such as server consolidation are a growing trend and contention for shared cache resources between workloads causes logical cache asymmetry, (b) future CMP platforms may be designed to be physically asymmetric in hardware due to die area pressure, process variability or power/performance efficiency. Our focus in this paper is to understand the performance implications of both logical as well as physical asymmetric caches on server consolidation. Based on real measurements of a state-of-the-art CMP processor running a server consolidation benchmark (vConsolidate) we compare the performance implications as a function of (a) symmetric caches, (b) virtually asymmetric caches, (c) physically asymmetric caches and (d) a combination of logically and physically asymmetric caches. We analyze the performance behavior in terms of (i) performance of each of the individual workloads being consolidated and (ii) architectural components such as CPI and MPI. We believe that this asymmetric cache study is the first of its kind and provides useful data/insights on cache characteristics of server consolidation. We also present inferences on future optimizations in the VMM scheduler as well as potential hardware techniques for future CMPs with cache asymmetry.
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页码:22 / 30
页数:9
相关论文
共 30 条
  • [1] *AMD INC, AMD MULT PROC
  • [2] [Anonymous], P 13 INT C PAR ARCH
  • [3] [Anonymous], P ACM S OP SYST PRIN
  • [4] [Anonymous], P USENIX ANN TECHN C
  • [5] APPARAO P, 2007, 2 WORKSH DES ARCH SI
  • [6] BARROSSO L, 1998, ACM SIGARCHI COM JUN
  • [7] CASAZZA JP, INTEL TECHNOLOGY J, V10
  • [8] Chandra D., 2005, 11 INT S HIGH PERF C
  • [9] GUPTA D, XENMON QOS MONITORIN
  • [10] *INT, 2005, INT VIRT TECHN SPEC