6.1 GHz 4.6 mW CMOS divide-by-55/56 prescaler

被引：5

作者：

Yu, X. P. ^{[1
]}

Lim, W. M. ^{[2
]}

Do, M. A. ^{[2
]}

Yan, X. L. ^{[1
]}

Yeo, K. S. ^{[2
]}

机构：

[1] Zhejiang Univ, Inst VLSI Design, Hangzhou, Zhejiang, Peoples R China

[2] Nanyang Technol Univ, Sch EEE, Singapore, Singapore

来源：

ELECTRONICS LETTERS | 2008年 / 44卷 / 24期

关键词：

D O I：

10.1049/el:20081871

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A divide-by-55/56 phase switching prescaler based on odd phase signals is proposed. The odd phase signals for phase switching are generated by a divide-by-7 injection-locked frequency divider. A simple topology with a high operating frequency and a low power consumption is obtained. Implemented with a standard 0.18 mu m CMOS process, the prescaler is able to work from 3.2 to 6.1 GHz with a maximum measured power consumption of 4.6 mW from a 1.8 V supply voltage.

引用

页码：1402 / 1403

页数：2

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