Modeling Superscalar Processor Memory-Level Parallelism

被引：9

作者：

Van den Steen, Sam ^{[1
]}

Eeckhout, Lieven ^{[1
]}

机构：

[1] Univ Ghent, Ghent, Belgium

来源：

IEEE COMPUTER ARCHITECTURE LETTERS | 2018年 / 17卷 / 01期

关键词：

Modeling; memory level parallelism (MLP); micro-architecture;

D O I：

10.1109/LCA.2017.2701370

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes an analytical model to predict Memory-Level Parallelism (MLP) in a superscalar processor. We profile the workload once and measure a set of distributions to characterize the workload's inherent memory behavior. We subsequently generate a virtual instruction stream, over which we then process an abstract MLP model to predict MLP for a particular micro-architecture with a given ROB size, LLC size, MSHR size and stride-based prefetcher. Experimental evaluation reports an improvement in modeling error from 16.9 percent for previous work to 3.6 percent on average for the proposed model.

引用

页码：9 / 12

页数：4

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