Low-Power AES Design Using Parallel Architecture

被引：0

作者：

Choi, Hyun Suk ^{[1
]}

Choi, Joong Hyan ^{[1
]}

Kim, Jong Tae ^{[1
]}

机构：

[1] Sungkyunkwan Univ, Sch Informat & Commun Engn, Suwon, South Korea

来源：

ICHIT 2008: INTERNATIONAL CONFERENCE ON CONVERGENCE AND HYBRID INFORMATION TECHNOLOGY, PROCEEDINGS | 2008年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper presents a design of AES(Advanced Encryption Standard) with parallel architecture. Proposed architecture maintains throughput as it is but consumes lower power than the original architecture by using 112 clock-rate and reducing supply voltage. Models were designed using VHDL and verified by both functional and gate-level simulation. They were logically synthesized using 0.25um, 90nm cell library by Synopsys Design compiler. Power consumption was computed by Synopsys PrimePower.

引用

页码：413 / 416

页数：4