A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver

被引：14

作者：

Lakdawala, Hasnain ^{[1
]}

Schaecher, Mark ^{[2
]}

Fu, Chang-Tsung ^{[1
]}

Limaye, Rahul ^{[3
]}

Duster, Jon ^{[1
]}

Tan, Yulin ^{[1
]}

Balankutty, Ajay ^{[1
]}

Alpman, Erkan ^{[1
]}

Lee, Chun C. ^{[1
]}

Khoa Minh Nguyen ^{[1
]}

Lee, Hyung-Jin ^{[1
]}

Ravi, Ashoke ^{[1
]}

Suzuki, Satoshi ^{[1
]}

Carlton, Brent R. ^{[1
]}

Kim, Hyung Seok ^{[1
]}

Verhelst, Marian ^{[1
]}

Pellerano, Stefano ^{[1
]}

Kim, Tong ^{[2
]}

Venkatesan, Satish ^{[3
]}

Srivastava, Durgesh ^{[3
]}

Vandervoorn, Peter ^{[1
]}

Rizk, Jad ^{[1
]}

Jan, Chia-Hong ^{[1
]}

Ramamurthy, Sunder ^{[3
]}

Yavatkar, Raj ^{[1
]}

Soumyanath, Krishnamurthy ^{[1
]}

机构：

[1] Intel Corp, Hillsboro, OR 97124 USA

[2] Intel Corp, Chandler, AZ 85226 USA

[3] Intel Corp, Santa Clara, CA 95054 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2013年 / 48卷 / 01期

关键词：

Clock generation; CMOS low noise amplifier; CMOS power amplifier; network on chip; RF circuit design; system fabric; system on chip;

D O I：

10.1109/JSSC.2012.2222812

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An x86 standard operating system compliant System-on-Chip (SoC) with a dual core ATOM processor and a custom interconnect fabric to enable modular design is presented. The 32 nm SoC includes integrated PCI-e Gen 2, DDR3, legacy I/O, voltage regulators, clock generation, power management, memory controller and RF portion of a WiFi transceiver in a 32 nm high-k/metal-gate RF CMOS process with high resistivity substrate. The integrated RF transceiver for 2.4 GHz 802.11g operation achieves a receive sensitivity of -74 dBm, -8 dBm IIP3 and a transmit output power of 20.3 dBm (-25 dB EVM) at 14% TX RF efficiency.

引用

页码：91 / 103

页数：13

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