Memory Compact High-Speed QC-LDPC Decoder

In this paper, compact memory strategies for partially parallel Quasi-cyclic LDPC (QC-LDPC) decoder architecture are proposed. By compacting several adjacent rows hard decisions and extrinsic messages into one memory entry, which not only reduces the number of memory banks for hard decisions, but also facilitates multiple data accesses per clock cycle, the throughput of the decoder is increased. We demonstrate significant benefits of using the proposed techniques with an FPGA implementation of a CCSDS LDPC decoder on Xilinx XC5VLX330 device. It shows that our decoder can operate at a maximum frequency of 250 MHz after place and route and achieve a throughput up to 2 Ghps at 14 iterations.