Efficient Security Monitoring with the Core Debug Interface in an Embedded Processor

被引:19
作者
Lee, Jinyong [1 ,2 ]
Heo, Ingoo [1 ,2 ]
Lee, Yongje [1 ,2 ,3 ]
Paek, Yunheung [1 ,2 ]
机构
[1] Seoul Natl Univ, Dept Elect & Comp Engn, 1 Gwanak Ro, Seoul, South Korea
[2] Seoul Natl Univ, ISRC, 1 Gwanak Ro, Seoul, South Korea
[3] Samsung Elect Co Ltd, Suwon, South Korea
基金
新加坡国家研究基金会;
关键词
Core debug interface (CDI); security monitoring; dynamic information flow tracking (DIFT); code reuse attack detection; HARDWARE ACCELERATION; PROTECTION;
D O I
10.1145/2907611
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
For decades, various concepts in security monitoring have been proposed. In principle, they all in common in regard to the monitoring of the execution behavior of a program (e.g., control-flow or dataflow) running on the machine to find symptoms of attacks. Among the proposed monitoring schemes, software-based ones are known for their adaptability on the commercial products, but there have been concerns that they may suffer from nonnegligible runtime overhead. On the other hand, hardware-based solutions are recognized for their high performance. However, most of them have an inherent problem in that they usually mandate drastic changes to the internal processor architecture. More recent ones have strived to minimize such modifications by employing external hardware security monitors in the system. However, these approaches intrinsically suffer from the overhead caused by communication between the host and the external monitor. Our solution also relies on external hardware for security monitoring, but unlike the others, ours tackles the communication overhead by using the core debug interface (CDI), which is readily available in most commercial processors for debugging. We build our system simply by plugging our monitoring hardware into the processor via CDI, precluding the need for altering the processor internals. To validate the effectiveness of our approach, we implement two well-known monitoring techniques on our proposed framework: dynamic information flow tracking and branch regulation. The experimental results on our FPGA prototype show that our external hardware monitors efficiently perform monitoring tasks with negligible performance overhead, mainly with thanks to the support of CDI, which helps us reduce communication costs substantially.
引用
收藏
页数:29
相关论文
共 69 条
  • [1] [Anonymous], THESIS
  • [2] [Anonymous], 2003, Address Space Layout Randomization (ASLR)
  • [3] [Anonymous], **NON-TRADITIONAL**
  • [4] [Anonymous], 2005, NDSS
  • [5] [Anonymous], 2005, P 12 ACM C COMP COMM
  • [6] [Anonymous], 2012, P 2012 INT C DEPENDA, DOI DOI 10.1109/DSN.2012.6263958
  • [7] ARM, 1999, Technical report
  • [8] ARM Limited, 2011, EMB TRAC MACR ARCH S
  • [9] ARM Ltd, 2013, 0029D ARM IHI
  • [10] Bellardo J, 2003, USENIX ASSOCIATION PROCEEDINGS OF THE 12TH USENIX SECURITY SYMPOSIUM, P15