High performance CMOS static logic circuit design

被引：0
|
作者：
Kuo, KC [1 ]
Carlson, BS [1 ]
机构：
[1] IBM Corp, Boston Design Ctr, Lowell, MA USA
来源：
PROCEEDINGS OF THE 44TH IEEE 2001 MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2 | 2001年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
A high performance CMOS Static Logic implemented by a new circuit technique is presented. The gate outputs are preconditioned to minimize delay using a new clocking scheme and circuit design. The simulated CLA circuit shows that the average power-delay product is 1.62 times smaller than the static implementations for 0.25mum process.
引用
收藏
页码：598 / 601
页数：4
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