A flexible SRAM compiler for embedded application

被引：0

作者：

Liu, Y ^{[1
]}

Gao, ZQ ^{[1
]}

机构：

[1] Tsing Hua Univ, Inst Elect, Beijing 100084, Peoples R China

来源：

SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1 AND 2, PROCEEDINGS | 2001年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

SRAM Compiler uses predefined building blocks or leaf cells and connectivity information to compile SRAMs of user-specified size. In this paper a high-speed embedded SRAM Compiler is described. It is based on TSMC's 0.5 mum CMOS process. It can compile both single-port and dual-port SRAMs. SRAM is a completely synchronous architecture with a maximal capacity 16k* 64=1Mb bits. The compiler generates the layout, behavioral level models, schematic symbols, and a layout abstraction to place and route, The program in Skill language can automatically complete the creation of all the models in different levels. The SRAM Compiler has a friendly user interface. Users can specify the necessary parameters and then get all the results. The SRAM Compiler can be easily integrated into Cadence and other CAD frameworks.

引用

页码：213 / 216

页数：4