Impact of trap charge and temperature on DC and Analog/RF performances of hetero structure overlapped PNPN tunnel FET

Impact of interface trap charges (ITCs) as well as temperature on the performance of a proposed dual dielectric constant spacer source/drain, overlapped double gate tunnel FET with a source pocket was investigated using two-dimensional Technology Computer-Aided Design (TCAD) device simulator. The proposed device is Si-based with Germanium as the source material, SiGe as a pocket material, and has a high-k gate dielectric. Its performance in terms of DC and analog/RF parameters vis-a-vis a conventional double gate PNPN TFET was compared. The device shows better results than the conventional one with an ON current of 1.71x10(-3) A/mu m, ON-OFF current ratio 10(11), and subthreshold swing of 45 mV/decade. The study was focused on the analysis of the electric field, transfer characteristics, transconductance (g(m)), output conductance (g(d)), parasitic capacitances, gain-bandwidth product (GBP), cut off frequency (f(T)) for both the damaged (presence of donor/acceptor interface trap charges) and undamaged (no trap) conditions. The study revealed that the proposed structure is more immune to the interfacial trap charges as compared to the conventional device. Apart from this, the analysis shows a degradation of subthreshold swing (SS) and OFF current (I-OFF) at elevated temperatures.