Measurement and analysis of thermal stresses in 3D integrated structures containing through-silicon-vias

Three-dimensional (3-D) integration with through-silicon-vias (TSVs) has emerged as an effective approach to overcome the wiring limit beyond the 32 nm technology node. Due to the mismatch of thermal expansion between the via material and Si, thermal stresses ubiquitously exist in the integrated 3-D structures. The thermal stresses can be significant to raise serious reliability issues, such as TSV extrusion and mobility degradation of logic devices. To understand the characteristics of the thermal stresses in TSVs, experimental measurements and numerical analysis are presented in this work. A precision wafer curvature technique was used together with micro-Raman spectroscopy to form a complementary approach to characterize the deformation and stresses in the TSV structures. The microstructures of the Cu vias were analyzed to provide insights to the deformation mechanisms. Guided by the experimental observations, finite element analysis was performed to analyze the thermal stresses taking into account the elastic anisotropy of Si and the plasticity of Cu. It was found that plastic deformation is localized within the Cu vias near the via/Si interface and may play an important role in TSV extrusion. Finally, the effect of thermal stresses on carrier mobility was investigated to evaluate the keep-out zone (KOZ) for logic devices near the TSVs. (C) 2012 Elsevier Ltd. All rights reserved.