Hardware-efficient phase-detection technique for digital clock and data recovery

被引：1

作者：

Zargaran-Yazd, A. ^{[1
]}

Keikhosravy, K. ^{[1
]}

Rashtian, H. ^{[1
]}

Mirabbasi, S. ^{[1
]}

机构：

[1] Univ British Columbia, Dept Elect & Comp Engn, Vancouver, BC V5Z 1M9, Canada

来源：

ELECTRONICS LETTERS | 2013年 / 49卷 / 01期

基金：

加拿大自然科学与工程研究理事会;

关键词：

Decision threshold - Digital clocks - Frequency detection - Hardware efficiency - Phase detection technique - Proof of concept - Sampling-based - Timing information;

D O I：

10.1049/el.2012.3722

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A phase-detection technique for digital clock and data recovery (CDR) in multi-Gbit/s serial links is presented. Compared to conventional sampling-based receivers, hardware efficiency at the system-level is achieved by extracting timing information from analysing the occurrence of certain patterns at the output of four comparators. The arrangement of the decision threshold and sampling time of these comparators is discussed, and the phase and frequency detection characteristic of such an arrangement is evaluated. The technique is validated through a proof-of-concept 12.5 Gbit/s CDR chip that is fabricated in 90nm CMOS.

引用

页码：20 / 21

页数：2