Development of fine pitch interconnections for 3D integrated circuits

被引：0

作者：

Bana, F. ^{[1
]}

Gamier, A. ^{[1
]}

Bresson, N. ^{[1
]}

Ponthenier, F. ^{[1
,2
]}

Loiodice, P. ^{[1
,2
]}

Cosset, F. ^{[1
,2
]}

Jouve, A. ^{[1
]}

Lattard, D. ^{[1
]}

Cheramy, S. ^{[1
]}

机构：

[1] CEA, LETI, MINATEC Campus,17 Rue Martyrs, F-38054 Grenoble 9, France

[2] STMicroelectronics, 850 Rue Jean Monnet, F-38926 Crolles, France

来源：

2016 6TH ELECTRONIC SYSTEM-INTEGRATION TECHNOLOGY CONFERENCE (ESTC) | 2016年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

As the electronic devices miniaturization roadmap trend is pursuing, 3D technologies have also emerged and appeared as one serious option for the next generation of semiconductors industry. The purpose of this paper is to introduce the complete development of fine pitch microbumps and micropillars for chip to wafer interconnections on 300 mm wafers using industrial tools and with already existing process. Our goal is to use production process and materials to simplify industry transfer. Good morphological and electrical results showed a process robustness that may he suitable for an industrial approach.

引用

页数：6

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