A 15-Bit 85 MS/s Hybrid Flash-SAR ADC in 90-nm CMOS

被引：3

作者：

Razzaq, Anas ^{[1
]}

Chaudhry, Shabbir Majeed ^{[2
]}

机构：

[1] COMSATS Inst Informat Technol, Dept Elect Engn, Wah Campus, Wah, Pakistan

[2] Univ Engn & Technol, Dept Elect Engn, Taxila, Pakistan

来源：

CIRCUITS SYSTEMS AND SIGNAL PROCESSING | 2018年 / 37卷 / 04期

关键词：

ADC; Flash ADC; SAR ADC; Hybrid ADC; Tri-level; Split capacitor; 65 NM CMOS; BIOMEDICAL APPLICATIONS; FJ/CONVERSION-STEP; SWITCHING SCHEME; PIPELINED ADC; ENERGY; CALIBRATION; CONVERSION;

D O I：

10.1007/s00034-017-0629-z

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 15-bit, 85 MS/s hybrid flash-SAR ADC is presented. The proposed design combines modified tri-level switching technique with split capacitor technique to improve the power efficiency and sampling rate of the SAR block. The sampling switch was designed to achieve reduced settling time for DAC. Modified encoder block was used in flash ADC block and PMOS resistive ladder was used for better matching and linearity. To overcome high-frequency noise jitters in resistive ladder, parallel capacitors were added which act as low-pass filter. At 85 MS/s device consumes 650 uW and achieved an SNDR of 74.3 dB, ENOB of 12.06 with SFDR of 89 dBc. The proposed ADC is implemented in 1P-9M low K 90-nm CMOS process technology and occupies a chip area of 720 um 195 um.

引用

页码：1452 / 1478

页数：27

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