Algorithm-based low-power VLSI architecture for 2-D mesh video-object motion tracking

This paper presents an algorithm-based low-power VLSI architecture for video object (VO) motion tracking. The new architecture uses a novel hierarchical adaptive structured mesh topology. The structured mesh offers a significant reduction in the number of bits that describe the mesh topology. The motion of the mesh nodes represents the deformation of the VO. The motion compensation is performed using a multi plication-free algorithm for affine transformation, which significantly reduces the complexity of the decoder architecture. Moreover, pipelining the affine unit contributes a considerable savings of power. The VO motion-tracking architecture is based on a new algorithm for tracking a VO. It consists of two main parts: a video object motion-estimation unit (VOME) and a video object motion-compensation unit (VOMC). The VOME processes two consequent frames to generate a hierarchical adaptive structured mesh and the motion vectors of the mesh nodes. It implements parallel block matching motion-estimation units to optimize the latency. The VOMC processes a reference frame, mesh nodes, and motion vectors to predict a video frame. It implements parallel threads in which each thread implements a pipelined chain of scalable affine units. This motion-compensation algorithm allows the use of one simple warping unit to map a hierarchical structure. The affine unit warps the texture of a patch at any level of hierarchical mesh independently. The processor uses a memory serialization unit, which interfaces the memory to the parallel units. The architecture has been prototyped using top-down low-power design methodology. The performance analysis shows that this processor can be used in online object-based video applications such as in MPEG-4 and VRML.