A 10-Bit 50-MS/s 11.9μW SAR ADC with CM Biased Capacitor Switching Method

被引：0

作者：

Naidu, Pragada V. Satya Challayya ^{[1
]}

Chaudhary, Priyanka ^{[1
]}

Anudeep, Manchikatla ^{[1
]}

Kumar, Ashish ^{[1
]}

机构：

[1] Amity Univ, Dept Elect & Commun Engn, Noida, Uttar Pradesh, India

来源：

2016 INTERNATIONAL CONFERENCE ON INVENTIVE COMPUTATION TECHNOLOGIES (ICICT), VOL 1 | 2016年

关键词：

SAR; ADC; DAC; SNDR; INL; DNL; FOM etc;

D O I：

暂无

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

SAR ADC architecture is mainly based on the CMOS technology and Op-amp free. In this paper, designed a SAR ADC with 10 Bit 50MS/s using CM biased Switching Method in 180nm CMOS technology. The ADC is analyzed using Nodal Analysis method and calculated different dynamic parameters like ENOB, SNDR, INL, DNL, FOM etc. These are simulated using HSPICE, Spice Explorer, CSCOPE and MATLAB software's. Simulation results says that the ADC consumes 11.89 mu W at sampling frequency rate of 50MS/s. The Effective number of Bits (ENOB) is 9.65, Signal to noise and distortion(SINAD) is 59.89 dB and Figure of Merit of ADC is 8.9 fJ/conversion per 1.8 V.

引用

页码：540 / 545

页数：6

共 49 条

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