FPGA HARDWARE DESIGN, SIMULATION AND SYNTHESIS FOR A INDEPENDENT COMPONENT ANALYSIS ALGORITHM USING SYSTEM-LEVEL DESIGN SOFTWARE

被引：0

作者：

Oliveira da Silva, Alan Paulo ^{[1
]}

Guimaraes Guerreiro, Ana Maria ^{[1
]}

Doria Neto, Adriao Duarte ^{[1
]}

机构：

[1] Univ Fed Rio Grande do Norte, UFRN CT PPgEEC, Ctr Technol, Campus Univ, BR-59072970 Natal, RN, Brazil

来源：

IMCIC 2010: INTERNATIONAL MULTI-CONFERENCE ON COMPLEXITY, INFORMATICS AND CYBERNETICS, VOL II | 2010年

关键词：

ICA; FPGA;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this work we proposed the design, simulation and synthesis of a hardware that performs the Independent Component Analysis (ICA) in a reconfigurable hardware platform, more specifically a FPGA. The simulation of the hardware was done by models implemented in Simulink environment and the synthesis was possible through the Altera system-level design software DSP Builder, that contains specific FPGA blocks that can be synthesized in hardware. In order to validate the hardware, manually generated data and real electroencephalogram signals were used in the experiments.

引用

页码：202 / 207

页数：6

共 37 条

[21] Design of a hardware/software FPGA-based driver system for a large area high resolution CCD image sensor
Chen Y.
Xu W.
Zhao R.
Chen X.
Photonic Sensors, 2014, 4 (03) : 274 - 280
[22] Hardware/Software Co-Design of an Accelerator for FV Homomorphic Encryption Scheme Using Karatsuba Algorithm
Migliore, Vincent
Real, Maria Mendez
Lapotre, Vianney
Tisserand, Arnaud
Fontaine, Caroline
Gogniat, Guy
IEEE TRANSACTIONS ON COMPUTERS, 2018, 67 (03) : 335 - 347
[23] Design of a FPGA Hardware Architecture to Detect Real-time Moving Objects Using the Background Subtraction Algorithm
Ren, Xin
Wang, Yu
PROCEEDINGS OF 2016 5TH INTERNATIONAL CONFERENCE ON COMPUTER SCIENCE AND NETWORK TECHNOLOGY (ICCSNT), 2016, : 428 - 433
[24] Hardware-Efficient Implementation of Principal Component Analysis Using High-Level Synthesis
Kumar, Venkata Siva K.
Sabat, Samrat L.
10TH INTERNATIONAL CONFERENCE ON ELECTRONICS, COMPUTING AND COMMUNICATION TECHNOLOGIES, CONECCT 2024, 2024,
[25] FPGA Design of Transposed Convolutions for Deep Learning Using High-Level Synthesis
Sestito, Cristian
Perri, Stefania
Stewart, Robert
JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2023, 95 (10): : 1245 - 1263
[26] Hardware/Software Co-Design of a Traffic Sign Recognition System Using Zynq FPGAs
Han, Yan
Virupakshappa, Kushal
Pinto, Esdras Vitor Silva
Oruklu, Erdal
ELECTRONICS, 2015, 4 (04) : 1062 - 1089
[27] Design of an FPGA-Based RTL-Level CAN IP Using Functional Simulation for FCC of a Small UAV System
Choe, Won Seop
Han, Dong In
Min, Chan Oh
Kim, Sang Man
Kim, Young Sik
Lee, Dae Woo
Lee, Ha-Joon
INTERNATIONAL JOURNAL OF AERONAUTICAL AND SPACE SCIENCES, 2017, 18 (04) : 675 - 687
[28] System Generator Model-Based FPGA Design Optimization and Hardware Co-simulation for Lorenz Chaotic Generator
Zhang, Lei
2017 2ND ASIA-PACIFIC CONFERENCE ON INTELLIGENT ROBOT SYSTEMS (ACIRS), 2017, : 170 - 174
[29] Min-Sum Algorithm Based Efficient High Level Methodology for Design, Simulation and Hardware implementation of LDPC Decoders
Ait Madi, Abdessalam
Ahaitouf, Ali
Mansouri, Anas
2012 SECOND INTERNATIONAL CONFERENCE ON INNOVATIVE COMPUTING TECHNOLOGY (INTECH), 2012, : 210 - 215
[30] A hardware/software co-design approach to prototype 6G mobile applications inside the GNU Radio SDR Ecosystem using FPGA hardware accelerators
Karle, Christian
Kreutzer, Marius
Pfau, Johannes
Becker, Jurgen
PROCEEDINGS OF THE 12TH INTERNATIONAL SYMPOSIUM ON HIGHLY EFFICIENT ACCELERATORS AND RECONFIGURABLE TECHNOLOGIES, HEART 2022, 2022, : 33 - 41

← 1 2 3 4 →