A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells

被引：4

作者：

Okumura, Shunsuke ^{[1
]}

Yoshimoto, Shusuke ^{[1
]}

Kawaguchi, Hiroshi ^{[1
]}

Yoshimoto, Masahiko ^{[1
,2
]}

机构：

[1] Kobe Univ, Kobe, Hyogo 6578501, Japan

[2] JST CREST, Tokyo 1020076, Japan

来源：

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | 2012年 / E95A卷 / 12期

关键词：

SRAM; chip ID; physical unclonable function (PUF);

D O I：

10.1587/transfun.E95.A.2226

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We propose a chip identification (ID) generating scheme with random variation of transistor characteristics in SRAM bitcells. In the proposed scheme, a unique fingerprint is generated by grounding both bitlines in write operations. Through minor modifications, this scheme can be implemented for existing SRAMs. It has high speed, and it can be implemented in a very small area overhead. The generated fingerprint mainly reflects threshold voltages of load transistors in the bitcells. We fabricated test chips in a 65-nm process and obtained 12,288 sets of unique 128-bit fingerprints, which are evaluated in this paper. The failure rate of the IDs is found to be 2.1 x 10(-12).

引用

页码：2226 / 2233

页数：8

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