Sigma-delta ADC with reduced sample rate multibit quantizer

被引：10

作者：

Qin, W ^{[1
]}

Hu, B ^{[1
]}

Ling, XT ^{[1
]}

机构：

[1] Fudan Univ, ASIC & Syst State Key Lab, Shanghai 200433, Peoples R China

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | 1999年 / 46卷 / 06期

关键词：

analog-to-digital converters; oversampling converters; sigma-delta modulation;

D O I：

10.1109/82.769792

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Based on the well-known Leslie-Singh architecture [1], a new cascaded sigma-delta analog-to-digital conversion (ADC) architecture is proposed. It incorporates a multihit quantizer whose sample rate can be significantly lower than the full oversampling speed of the sigma-delta modulator. Simulation results and comparison with other architectures are given, The architecture can be a good choice to extend the use of sigma-delta ADC to high bandwidth applications.

引用

页码：824 / 828

页数：5

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