Multi-bit Sigma-Delta TDC Architecture with Improved Linearity

被引：9

作者：

Uemori, Satoshi ^{[1
]}

Ishii, Masamichi ^{[1
]}

Kobayashi, Haruo ^{[1
]}

Hirabayashi, Daiki ^{[1
]}

Arakawa, Yuta ^{[1
]}

Doi, Yuta ^{[1
]}

Kobayashi, Osamu ^{[2
]}

Matsuura, Tatsuji ^{[1
]}

Niitsu, Kiichi ^{[3
]}

Yano, Yuji ^{[2
]}

Gake, Tatsuhiro ^{[2
]}

Yamaguchi, Takahiro J. ^{[1
]}

Takai, Nobukazu ^{[1
]}

机构：

[1] Gunma Univ, Div Elect & Informat, Kiryu, Gunma 3768515, Japan

[2] STARC, Yokohama, Kanagawa 2220033, Japan

[3] Nagoya Univ, Grad Sch Engn, Dept Elect Engn & Comp Sci, Nagoya, Aichi 4648603, Japan

来源：

JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS | 2013年 / 29卷 / 06期

关键词：

Time-to-digital converter; Time measurement; Sigma-delta modulation; Multi-bit; Calibration; High-speed I/O interface circuit testing;

D O I：

10.1007/s10836-013-5408-6

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes the architecture and principles of operation of sigma-delta ( I I") pound time-to-digital converters (TDC) for high-speed I/O interface circuit test applications. In particular, we describe multi-bit I I" pound TDC architectures; they offer good accuracy with short testing time. However, mismatches among delay cells in delay lines degrade their linearity. Here we propose two methods to improve the overall TDC linearity: a data-weighted-average (DWA) algorithm, and a self-calibration method that measures delay values using a ring oscillator circuit. Our Matlab simulation results demonstrate the effectiveness of these approaches.

引用

页码：879 / 892

页数：14

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