Design of the HP PA 7200 CPU

被引:0
|
作者
Chan, KK
Hay, CC
Keller, JR
Kurpanek, GP
Schumacher, FX
Zheng, J
机构
来源
HEWLETT-PACKARD JOURNAL | 1996年 / 47卷 / 01期
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The PA 7200 processor chip is specifically designed to give enhanced performance in a four-way multiprocessor system without additional interface circuits. It has a new data cache organization, a prefetching mechanism, and two integer ALUs for general integer superscalar execution.
引用
收藏
页码:25 / 33
页数:9
相关论文
共 50 条
  • [2] Verification, characterization, and debugging of the HP PA 7200 processor
    Alexander, TB
    Dickey, KA
    Goldberg, DN
    LaFetra, RV
    McGee, JR
    Noordeen, N
    Prakash, A
    HEWLETT-PACKARD JOURNAL, 1996, 47 (01): : 34 - 43
  • [3] The HP PA-8000 RISC CPU
    Kumar, A
    IEEE MICRO, 1997, 17 (02) : 27 - 32
  • [5] Design of cache test hardware on the HP PA8500
    Brauch, J
    Fleischman, J
    ITC - INTERNATIONAL TEST CONFERENCE 1997, PROCEEDINGS: INTEGRATING MILITARY AND COMMERCIAL COMMUNICATIONS FOR THE NEXT CENTURY, 1997, : 286 - 293
  • [6] Functional design of the HP PA 7300LC processor
    Johnson, L
    Undy, SR
    HEWLETT-PACKARD JOURNAL, 1997, 48 (03): : 48 - 60
  • [7] Design of cache test hardware on the HP PA8500
    Brauch, J
    Fleischman, J
    IEEE DESIGN & TEST OF COMPUTERS, 1998, 15 (03): : 58 - 63
  • [8] Design methodologies and circuit design trade-offs for the HP PA 8000 processor
    Dorweiler, PJ
    Moore, FE
    Josephson, DD
    ColonBonet, GT
    HEWLETT-PACKARD JOURNAL, 1997, 48 (04): : 16 - 21
  • [9] 7200HP全回转拖轮研究与设计
    俞庆武
    港口科技, 2014, (01) : 19 - 22
  • [10] DESIGN VERIFICATION OF THE HP-9000 SERIES 700 PA-RISC WORKSTATIONS
    AHI, AM
    BURROUGHS, GD
    GORE, AB
    LAMAR, SW
    LIN, CYR
    WIEMANN, AL
    HEWLETT-PACKARD JOURNAL, 1992, 43 (04): : 34 - 42