HIGH GAIN AND LOW POWER DESIGN OF PREAMPLIFIER FOR CMOS COMPARATOR

被引：0
|
作者：
Choudhary, Shubham [1 ]
Bhat, Siddharth [1 ]
Selvakumar, J. [1 ]
机构：
[1] SRM Univ, ECE Dept, Madras, Tamil Nadu, India
来源：
2016 3RD INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND INTEGRATED NETWORKS (SPIN) | 2016年
关键词：
Pre-amplification; Cascode stage; High gain; Low power; AMPLIFIER;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, a low power and low noise pre-amplifier is designed for Analog to Digital Converter (ADC) operating with 1.2 V power supply. The pre-amplification technique is based on differential pair with cascode stage which provides very low power. The goal of achieving high gain and low power is achieved by operating the circuit in differential mode to get maximum gate to source voltage. The gain of feedback loop also helps to attain high gain. The proposed pre-amplifier is simulated in 90nm CMOS technology. The open loop DC gain of proposed pre-amplifier is 32 dB, the gain bandwidth product is 108 kHz with a phase margin of 62 degrees. The power consumption of proposed pre-amplifier is 3.3 mu W for 1.2 V power supply.
引用
收藏
页码：63 / 66
页数：4
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