Small-Signal Modeling of Active-Clamped ZVS Current-Fed Full-Bridge Isolated DC/DC Converter and Control System Implementation Using PSoC

被引：52

作者：

Prasanna, Udupi R. ^{[1
]}

Rathore, Akshay K. ^{[1
]}

机构：

[1] Natl Univ Singapore, Singapore 117576, Singapore

来源：

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS | 2014年 / 61卷 / 03期

关键词：

Active clamp; closed-loop control; current-fed dc/dc converter; high frequency (HF); small-signal model (SSM); DESIGN;

D O I：

10.1109/TIE.2013.2259784

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The small-signal analysis of an active-clamped zero-voltage-switching current-fed isolated dc/dc converter is presented in this paper. State-space averaging is used to derive the small-signal model. A closed-loop controller is designed to regulate the converter output over a wide range of power (1 : 10) and source voltage (1 : 2) with fixed frequency duty cycle modulation. Bode plots are presented using MATLAB and PSIM 9.0 to show the frequency response of the converter with and without a controller. The designed controller is implemented on the mixed-signal (analog and digital) processor Cypress Programmable System-on-Chip (PSoC) 5. All components are integrated in Cypress PSoC 5 which is compact, economical, and easily configurable. A 300-W converter prototype is developed and tested with the implemented controller to observe the performance of the system. Experimental results for step change in load for different input voltage conditions show the high performance of the controller, satisfactory transient performance of the converter, and voltage regulation with continued safe operation.

引用

页码：1253 / 1261

页数：9

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