Model predictive control for deeply pipelined field-programmable gate array implementation: algorithms and circuitry

被引:41
作者
Jerez, J. L. [1 ]
Ling, K. -V. [2 ]
Constantinides, G. A. [1 ]
Kerrigan, E. C. [1 ,3 ]
机构
[1] Univ London Imperial Coll Sci Technol & Med, Dept Elect & Elect Engn, London SW7 2AZ, England
[2] Nanyang Technol Univ, Sch Elect & Elect Engn, Singapore 639798, Singapore
[3] Univ London Imperial Coll Sci Technol & Med, Dept Aeronaut, London SW7 2AZ, England
基金
英国工程与自然科学研究理事会;
关键词
Embedded systems - Logic gates - Computation theory - Predictive control systems - Timing circuits - Field programmable gate arrays (FPGA) - Quadratic programming;
D O I
10.1049/iet-cta.2010.0441
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Model predictive control (MPC) is an optimisation-based scheme that imposes a real-time constraint on computing the solution of a quadratic programming (QP) problem. The implementation of MPC in fast embedded systems presents new technological challenges. In this paper we present a parameterised field-programmable gate array implementation of a customised QP solver for optimal control of linear processes with constraints, which can achieve substantial acceleration over a general purpose microprocessor, especially as the size of the optimisation problem grows. The focus is on exploiting the structure and accelerating the computational bottleneck in a primal-dual interior-point method. We then introduce a new MPC formulation that can take advantage of the novel computational opportunities, in the form of parallel computational channels, offered by the proposed pipelined architecture to improve performance even further. This highlights the importance of the interaction between the control theory and digital system design communities for the success of MPC in fast embedded systems.
引用
收藏
页码:1029 / 1041
页数:13
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