Trapping Time Characteristics of Carriers in a-InGaZnO Thin-Film Transistors Fabricated at Low Temperatures for Next-Generation Displays

The effect of low-temperature annealing treatment for various durations on the stability of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors was investigated. By this treatment, IGZO TFTs showed enhanced electrical characteristics and better stability under positive gate bias stress with increasing annealing time up to 18,000 s. For all V (G) stresses at different annealing times, the experimentally measured threshold voltage shift (Delta V (th)) as a function of stress time was precisely modeled with a stretched-exponential function. Delta V (th) was generated by carrier trapping, not by defect creation. It was verified that the decrease of interface trap state density (N (it)) and free carriers resulted in the decrease of Delta V (th) with increasing annealing time. However, the characteristic trapping time of the carriers increased up to 5.3 x 10(3) s with increasing annealing time to 7,200 s and then decreased, implying that the interface quality between active layer/insulator was deteriorated with further annealing. In this study, successful fabrication of IGZO TFTs by post treatment with optimized duration is demonstrated for flexible display applications.