High-speed Image Acquisition and Network Transmission System Based on FPGA

Through the study of the Camera Link interface protocol, the Ethernet protocol, and the VGA display sequence, the writer designs a high-speed image acquisition and network transmission system based on FPGA (Field-Programmable Gate Array) CMOS (Complementary Metal Oxide Semiconductor) and details the system structure as well. The system uses FPGA to drive CMOS image sensor for collecting the image data, and DDR3 module for data caching. Through controlling the Ethernet interface chip by the FPGA master control chip, the systems can achieve high-speed data transmission and transmit the image data to the upper computer for display or to the VGA (Video Graphics Array) for display on the screen. The system achieves high-speed image data acquisition, storage, remote transmission and display.