Simultaneous Guiding Template Optimization and Redundant via Insertion for Directed Self-Assembly

In sub-10 nm technology nodes, next generation lithography technologies are urgently required, and the diblock copolymer directed self-assembly (DSA) technology has shown its strong potential for contact/via layer fabrication. In addition, post-layout redundant via insertion has become a necessary step to guarantee sufficient yield and circuit reliability. However, existing redundant via insertion algorithms are not suitable for DSA since they could seriously deteriorate via manufacturability. In contrast, a sophisticated DSA-aware redundant via insertion algorithm may not only enhance circuit reliability but also improve DSA manufacturability. In this paper, we propose the first work of simultaneous guiding template optimization and redundant via insertion for DSA. Two integer linear programming (ILP)-based algorithms and an efficient graph-based approach are provided. The two ILP-based algorithms optimally maximize via manufacturability and the redundant via insertion rate. In addition, reduction techniques are presented to greatly improve the computational efficiency of ILP. For the graph-based approach, all feasible via patterns composed of original vias and redundant vias are identified. Then, the original problem is transformed into a graph formulation and efficiently optimized. Experimental results show that the ILP-based algorithms can find optimal solutions with reasonable computation time, and the graph-based algorithm can solve the problem much more efficiently and derive near-optimal solutions.