Design-Space Exploration of Ultra-Low Power CMOS Logic Gates in a 28 nm FD-SOI Technology

被引：0

作者：

Vohrmann, Marten ^{[1
]}

Geisler, Philippe ^{[1
]}

Jungeblut, Thorsten ^{[1
]}

Rueckert, Ulrich ^{[1
]}

机构：

[1] Bielefeld Univ, Cognitron & Sensor Syst Grp, CITEC, D-33619 Bielefeld, Germany

来源：

2017 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN (ECCTD) | 2017年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Logic gates for ultra-low voltages suffer from speed and robustness degradations, which are highly associated with the process technology. In this work a methodology for the automated design-space exploration of standard logic gates for a 28nm FD-SOI technology is shown. Comprehensive design space explorations of inverter and nand2 gates show the benefits of back-biasing at sub-threshold supply voltages. A comparison of Pareto points with a common energy consumption of 1 fJ shows that for the inverter minimum variation of 3.66% is achieved utilizing 4 stacking transistors (LVT type), while delay is increased by 21 %. For nand2 gates the standard CMOS implementations (LVT type) outperforms transmission gates and stacked transmission gates in terms of variation (3.84 %) and delay (2.99 ns).

引用

页数：4

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