Process Simulation of DRIE and its Application in Tapered TSV Fabrication

被引：0

作者：

Miao, Min ^{[1
]}

Liao, Hongguang ^{[1
]}

Wan, Xin ^{[1
]}

Zhao, Liwei ^{[1
]}

Guo, Yunxia ^{[1
]}

Jin, Yufeng ^{[1
]}

机构：

[1] Peking Univ, Natl Key Lab Micronano Fabricat Technol, Beijing 100871, Peoples R China

来源：

2008 INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING, VOLS 1 AND 2 | 2008年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

TSV (Through Silicon Via) has been widely welcomed as an enabling technology for three-dimensional integration in a package with high density. The developing of a drilling method for TSVs with tapered sections by experimental methodology can be a tedious task. The authors thus explore the possibility to simulate the process conditions effectively with an in-house developed simulator which utilize hybrid line and cell evolution algorithms. The micro-fabrication using the parameters obtained by the simulation has demonstrated TSVs with tapered sectional profiles and filled with electroplated coppers as expected, which validates the effectiveness of the simulated results.

引用

页码：256 / 259

页数：4

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