Multilevel symmetry-constraint generation for retargeting large analog layouts

被引:23
作者
Bhattacharya, Sambuddha [1 ]
Jangkrajamg, Nuttom [1 ]
Shi, C-J. Richard [1 ]
机构
[1] Univ Washington, Dept Elect Engn, Seattle, WA 98195 USA
基金
美国国家科学基金会;
关键词
analog integrated circuit (IC); device matching; IC layout; layout automation;
D O I
10.1109/TCAD.2005.855982
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The strong impact of layout intricacies on analog-circuit performance poses great challenges to analog layout automation. Recently, template-based methods have been shown to be effective in reuse-centric layout automation for CMOS analog blocks such as operational amplifiers. The layout-retargeting method first creates a template by extracting a set of constraints from an existing layout representation. From this template, new layouts are then generated corresponding to new technology processes and new device. specifications. For large analog layouts, however, this method results in an unmanageable template due to a tremendous increase in the number of constraints, especially those emerging from layout symmetries. In this paper, we present a new method of multilevel symmetry-constraint generation by utilizing the inherent circuit structure and hierarchy information from the extracted nedist. The method has been implemented in a layout-retargeting system called Intellectual Property Reuse-based Analog IC Layout (IPRAIL) and demonstrated 18 times reduction in the number of symmetry constraints required for retargeting an analog-to-digital converter layout. This enables our retargeting engine to successfully handle the complexities associated with large analog layouts. While manual relayout is known to take weeks, our layout-retargeting tool generates the target layout in hours and achieves comparable electrical performance.
引用
收藏
页码:945 / 960
页数:16
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