CASE: A Reliability Simulation Tool for Analog ICs

被引：0

作者：

Martin-Lloret, P. ^{[1
]}

Toro-Frias, A. ^{[1
]}

Castro-Lopez, R. ^{[1
]}

Roca, E. ^{[1
]}

Fernandez, F. V. ^{[1
]}

Martin-Martinez, J. ^{[2
]}

Rodriguez, R. ^{[2
]}

Nafria, M. ^{[2
]}

机构：

[1] Univ Seville, CSIC, IMSE CNM, Inst Microelect Sevilla, Seville, Spain

[2] Univ Autonoma Barcelona, Dept Engn Elect, Barcelona, Spain

来源：

2017 14TH INTERNATIONAL CONFERENCE ON SYNTHESIS, MODELING, ANALYSIS AND SIMULATION METHODS AND APPLICATIONS TO CIRCUIT DESIGN (SMACD) | 2017年

关键词：

reliability; process variability; aging; simulation flow; analog ICs; BTI; HCI;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

With the evolution in the scale of integration in ICs, aging-related problems are becoming more important and, nowadays, solutions to cope with these issues are not yet mature enough, especially in the field of analog circuit simulation. CASE, the novel simulator presented in this paper, can evaluate the impact of reliability effects in analog circuits through a stochastic physic-based model. The implemented simulation flow is accurate and efficient in terms of CPU. The two main improvements over currently reported and commercial tools, is that the simulator can simultaneously take into account both time-zero and time-dependent variability, and that an adaptive method, to account for the strong link between biasing and stress, can improve the accuracy while keeping acceptable CPU times.

引用

页数：4

共 10 条

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