An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput

被引：148

作者：

Kawahara, Akifumi ^{[1
]}

Azuma, Ryotaro ^{[1
]}

Ikeda, Yuuichirou ^{[1
]}

Kawai, Ken ^{[1
]}

Katoh, Yoshikazu ^{[1
]}

Hayakawa, Yukio ^{[1
]}

Tsuji, Kiyotaka ^{[1
]}

Yoneda, Shinichi ^{[1
]}

Himeno, Atsushi ^{[1
]}

Shimakawa, Kazuhiko ^{[1
]}

Takagi, Takeshi ^{[1
]}

Mikawa, Takumi ^{[1
]}

Aono, Kunitoshi ^{[1
]}

机构：

[1] Panasonic Corp, Kyoto 6018413, Japan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2013年 / 48卷 / 01期

关键词：

ReRAM; multi-layer; cross-point; resistive memory element; bidirectional diode; short bitline structure; multi-bit write architecture; write dummy cell; error check and correct; write throughput;

D O I：

10.1109/JSSC.2012.2215121

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An 8-Mb multi-layered cross-point resistive RAM (ReRAM) macro has been developed with 443 MB/s write throughput (64-bits parallel write per 17.2-ns cycle), which is almost twice as fast as competing methods. It uses the fast switching performance of TaOx ReRAM and a new write architecture to reduce the sneak current in a cross-point cell array structure based on an 0.18-mu m process. First, a bidirectional diode as a memory cell select element is developed to reduce the sneak current. Second, PMOS and NMOS are used select transistors in the source follower to realize stable switching for the selected cell in the multi-layered cross-point structure. Third, a hierarchical bitline (BL) structure is employed with a short bitline. Fourth, multi-bit write architecture is developed to realize fast write operation and to suppress the sneak current.

引用

页码：178 / 185

页数：8

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