Parallel Architectures for the kNN Classifier - Design of Soft IP Cores and FPGA Implementations

被引：23

作者：

Stamoulias, Ioannis ^{[1
]}

Manolakos, Elias S. ^{[1
]}

机构：

[1] Univ Athens, Dept Informat & Telecommun, Athens 15784, Greece

来源：

ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS | 2013年 / 13卷 / 02期

关键词：

Design; Architectures; classification; embedded systems design; VLSI array architectures; soft IP cores; k-nearest-neighbor classifier;

D O I：

10.1145/2514641.2514649

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We designed a variety of k-nearest-neighbor parallel architectures for FPGAs in the form of parameterizable soft IP cores. We show that they can be used to solve large classification problems with thousands of training vectors, or thousands of vector dimensions using a single FPGA, and achieve very high throughput. They can be used to flexibly synthesize architectures that also cover: 1NN classification (vector quantization), multishot queries (with different k), LOOCV cross-validation, and compare favorably to GPU implementations. To the best of our knowledge this is the first attempt to design flexible IP cores for the popular kNN classifier.

引用

页数：21