A 36.4dB SNDR @ 5GHz 1.25GS/s 7b 3.56mW Single-Channel SAR ADC in 28nm Bulk CMOS

被引：0
|
作者：
Ramkaj, Athanasios [1 ]
Strackx, Maarten [2 ]
Steyaert, Michiel [1 ]
Tavernier, Filip [1 ]
机构：
[1] Katholieke Univ Leuven, ESAT MICAS, Kasteelpk Arenberg 10, B-3001 Leuven, Belgium
[2] Bell Labs, Nokia, Antwerp, Belgium
来源：
ESSCIRC 2017 - 43RD IEEE EUROPEAN SOLID STATE CIRCUITS CONFERENCE | 2017年
关键词：
Successive approximation register; high sampling rate; high bandwidth; low power; bootstrapped input switch capacitive DAC (CDAC); dynamic comparator;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 1.25GS/s 7b single-channel SAR ADC is presented with an SNDR/SFDR of 41.4dB/51dB at low frequencies, while the SNDR/SFDR at Nyquist are 40.1dB/52dB and remain still 36.4dB/50.1dB at 5GHz. The high input frequency linearity is enabled by a fast bootstrap circuit for the input switch, while the high sampling rate, the highest among recently published >34dB SNDR single-channel SAR ADCs is achieved by a Triple-Tail dynamic comparator and a Unit-Switch-Plus-Cap (USPC) DAC. The prototype ADC in 28nm CMOS consumes only 3.56mW from a 1V supply, leading to a Walden FoM of 34.4fJ/conv-step at Nyquist for a core chip area of 0.0071mm(2).
引用
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页码：167 / 170
页数：4
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