Impact of circuit load on the ageing mode of VDMOS chips using 3D FEM Electro-thermal modelling

Currently a strong demand for robustness has emerged in all areas of power devices applications. Accordingly, phenomena at the origin of the failure mechanism must be studied. However, these phenomena are difficult to capture experimentally; hence, multi-physics 3D FEM simulations are strongly needed. Generally, these simulations are electro-thermal or electro-thermo-mechanical and the electrical part of these simulations are restricted to an imposed current flow through resistive materials. Nevertheless in real application the current level is in fact imposed by the circuit load. This paper deals with a methodology based on spice-electrical models coupled with 3D FEM thermal simulation to evaluate the impact of load (like bulb or Xenon automotive lighting device) which could lead to a short circuit