Computation of Seeds for LFSR-Based Diagnostic Test Generation

被引:12
作者
Pomeranz, Irith [1 ]
机构
[1] Purdue Univ, Sch Elect & Comp Engn, W Lafayette, IN 47907 USA
关键词
Defect diagnosis; diagnostic test generation; linear-feedback shift register (LFSR)-based test generation; ATPG;
D O I
10.1109/TCAD.2015.2459031
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper describes a procedure that computes seeds for linear-feedback shift register-based diagnostic test generation. A conventional process first computes test cubes, and then computes seeds that produce them by solving sets of linear equations. With this process, a seed may not exists for a given test cube. To address this issue, the procedure described in this paper produces seeds directly. Staring from a seed for fault detection, it modifies the seed such that the test it produces will distinguish a pair of faults. The procedure is applied in two modes. The first mode does not require diagnostic test cubes. In this mode, the procedure attempts to modify a seed for fault detection so as to lose the detection of one of the faults on one of the outputs where the faults are detected. The procedure thus uses the concept of test elimination that was used earlier for diagnostic test generation. The second mode is guided by a diagnostic test cube for a fault pair that needs to be distinguished. The procedure modifies a seed so as to reduce the distance between the test that the seed produces and the test cube. Without the requirement to match all the specified values of the test cube, the procedure can produce a seed for distinguishing the pair of faults even when a seed for the given test cube does not exist. Experimental results are presented to demonstrate the effectiveness of the procedure.
引用
收藏
页码:2004 / 2012
页数:9
相关论文
共 29 条
[1]  
Abramovici M., 1995, DIGITAL SYSTEMS TEST
[2]  
Acevedo O., 2012, 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2012), P233, DOI 10.1109/DFT.2012.6378229
[3]   A novel test generation methodology for adaptive diagnosis [J].
Adapa, Rajsekhar ;
Flanigan, Edward ;
Tragoudas, Spyros .
ISQED 2008: PROCEEDINGS OF THE NINTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2008, :242-245
[4]  
Alampally S, 2011, IEEE VLSI TEST SYMP, P285, DOI 10.1109/VTS.2011.5783735
[5]  
Bardell P. H., 1987, Built-In Test for VLSI: Pseudorandom Techniques
[6]   OPMISR: The foundation for compressed ATPG vectors [J].
Barnhart, C ;
Brunkhorst, V ;
Distler, F ;
Farnsworth, O ;
Keller, B ;
Koenemann, B .
INTERNATIONAL TEST CONFERENCE 2001, PROCEEDINGS, 2001, :748-757
[7]  
CAMURATI P, 1990, PROCEEDINGS : INTERNATIONAL TEST CONFERENCE 1990, P52, DOI 10.1109/TEST.1990.114000
[8]   Breaking the Test Application Time Barriers in Compression: Adaptive Scan - Cyclical (AS-C) [J].
Chandra, Anshuman ;
Saikia, Jyotirmoy ;
Kapur, Rohit .
2011 20TH ASIAN TEST SYMPOSIUM (ATS), 2011, :432-437
[9]   Diagnostic test-pattern generation targeting open-segment defects and its diagnosis flow [J].
Chen, Y. -H. ;
Chang, C. -L. ;
Wen, C. H. -P. .
IET COMPUTERS AND DIGITAL TECHNIQUES, 2012, 6 (03) :186-193
[10]   Enhancing Transition Fault Model for Delay Defect Diagnosis [J].
Cheng, Wu-Tung ;
Benware, Brady ;
Guo, Ruifeng ;
Tsai, Kun-Han ;
Kobayashi, Takeo ;
Maruo, Kazuyuki ;
Nakao, Michinobu ;
Fukui, Yoshiaki ;
Otake, Hideyuki .
PROCEEDINGS OF THE 17TH ASIAN TEST SYMPOSIUM, 2008, :179-+