A Fractional-N Frequency Divider for SSCG Using a Single Dual-Modulus Integer Divider and a Phase Interpolator

被引：0

作者：

Choi, Young-Ho ^{[1
]}

Sim, Jae-Yoon ^{[1
]}

Park, Hong-June ^{[1
,2
]}

机构：

[1] Pohang Univ Sci & Technol POSTECH, Dept Elect & Elect Engn, Pohang, South Korea

[2] Pohang Univ Sci & Technol POSTECH, Div IT Convers Engn, WCU Program, Pohang, South Korea

来源：

2012 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) | 2012年

基金：

新加坡国家研究基金会;

关键词：

Fractional-N frequency divider; peak sprectrum reduction; Spread Spectrum Clock Generator; SSCG; SPECTRUM CLOCK GENERATOR;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A fractional-N frequency divider for 2.5GHz SSCG is implemented by using a single 79/80 dual-modulus integer divider and a phase interpolator. The dual-modulus divider accepts one of the 4-phase 2.5GHz VCO outputs as input. The outputs of the dual-modulus divider is sampled by the 4-phase VCO outputs to generate 5-phase signals, which are used to generate a fractional-N divided signal with the division ratio 79+K/64 (K=0 similar to 64) by using a 1/16 phase interpolator and a phase rotator. The output jitter due to the quantization noise as in delta-sigma modulator (DSM) based divider is eliminated. An implementation of the SSCG using the proposed fractional-N divider in a 0.11 mu m CMOS process gives a chip area of 0.3 x 0.32mm(2), a power of 13.4mW at 1.2V.

引用

页码：68 / 71

页数：4

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