A Fractional-N Frequency Divider for SSCG Using a Single Dual-Modulus Integer Divider and a Phase Interpolator

A fractional-N frequency divider for 2.5GHz SSCG is implemented by using a single 79/80 dual-modulus integer divider and a phase interpolator. The dual-modulus divider accepts one of the 4-phase 2.5GHz VCO outputs as input. The outputs of the dual-modulus divider is sampled by the 4-phase VCO outputs to generate 5-phase signals, which are used to generate a fractional-N divided signal with the division ratio 79+K/64 (K=0 similar to 64) by using a 1/16 phase interpolator and a phase rotator. The output jitter due to the quantization noise as in delta-sigma modulator (DSM) based divider is eliminated. An implementation of the SSCG using the proposed fractional-N divider in a 0.11 mu m CMOS process gives a chip area of 0.3 x 0.32mm(2), a power of 13.4mW at 1.2V.