Design and Simulation of Steep-Slope Silicon-On-Insulator FETs using Negative Capacitance: Impact of Buried Oxide Thickness and Remnant Polarization

被引：0

作者：

Ota, Hiroyuki ^{[1
]}

Migita, Shinji ^{[1
]}

Hattori, Junichi ^{[1
]}

Fukuda, Koichi ^{[1
]}

Toriumi, Akira ^{[1
]}

机构：

[1] Natl Inst Adv Ind Sci & Technol, Tsukuba, Ibaraki 3058568, Japan

来源：

2016 IEEE 16TH INTERNATIONAL CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO) | 2016年

基金：

日本科学技术振兴机构;

关键词：

D O I：

暂无

中图分类号：

TB3 [工程材料学];

学科分类号：

0805 ; 080502 ;

摘要：

This paper discusses the importance of determining a suitable value of the buried oxide (BOX) thickness and remnant polarization in ferroelectric silicon-on-insulator FETs to attain a steep subthreshold swing (SS) by exploiting the negative capacitance effects. We reveal that a small value of remnant polarization P-r(3 mu C/cm(2) at most) and ultrathin BOX (< 10 nm) are key to realizing SS < 60 mV/decade.

引用

页码：770 / 772

页数：3

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