A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm Hi-k Metal Gate CMOS Technology

被引：24

作者：

Hamzaoglu, Fatih ^{[1
]}

Zhang, Kevin ^{[1
]}

Wang, Yih ^{[1
]}

Ahn, Hong Jo ^{[1
]}

Bhattacharya, Uddalak ^{[1
]}

Chen, Zhanping ^{[1
]}

Ng, Yong-Gee ^{[1
]}

Pavlov, Andrei ^{[1
]}

Smits, Ken ^{[2
]}

Bohr, Mark ^{[1
]}

机构：

[1] Intel Corp, Hillsboro, OR 97124 USA

[2] Intel Corp, Santa Clara, CA 95054 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2009年 / 44卷 / 01期

关键词：

Forward-body-bias; high-speed; leakage reduction; low-power; sleep transistor; Static-random-access-memory (SRAM); FLUCTUATIONS;

D O I：

10.1109/JSSC.2008.2007151

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A high-performance low-power 153 Mb SRAM is developed in 45 nm high-k Metal Gate technology. Dynamic SRAM PMOS forward-body-bias (FBB) and Active-Controlled SRAM VCC in Sleep are integrated in the design to lower Active-VCCmin and Standby Leakage, respectively. FBB improves the Active-VCCmin by up to 75 mV, and Active-Controlled SRAM VCC distribution tightened by 100 mV, both of which result in further power reduction. A 0.346 mu m(2) 6T-SRAM bit-cell is used which is optimized for VCCmin, performance, leakage and area. The design operates at high-speed over a wide voltage range, and has a maximum frequency of 3.8 GHz at 1.1 V. The 16 KB Subarray was also used as the building block in on-die 6 MB Cache for Intel Core 2 Duo CPU in 45 nm technology.

引用

页码：148 / 154

页数：7

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