T-CREST: Time-predictable multi-core architecture for embedded systems

被引：139

作者：

Schoeberl, Martin ^{[1
]}

Abbaspour, Sahar ^{[1
]}

Akesson, Benny ^{[2
]}

Audsley, Neil ^{[3
]}

Capasso, Raffaele ^{[4
]}

Garside, Jamie ^{[3
]}

Goossens, Kees ^{[5
]}

Goossens, Sven ^{[5
]}

Hansen, Scott ^{[6
]}

Heckmann, Reinhold ^{[7
]}

Hepp, Stefan ^{[8
]}

Huber, Benedikt ^{[8
]}

Jordan, Alexander ^{[1
]}

Kasapaki, Evangelia ^{[1
]}

Knoop, Jens ^{[8
]}

Li, Yonghui ^{[5
]}

Prokesch, Daniel ^{[8
]}

Puffitsch, Wolfgang ^{[1
]}

Puschner, Peter ^{[8
]}

Rocha, Andre ^{[9
]}

Silva, Claudio ^{[9
]}

Sparso, Jens ^{[1
]}

Tocchi, Alessandro ^{[4
]}

机构：

[1] Tech Univ Denmark, Lyngby, Denmark

[2] Czech Tech Univ, CR-16635 Prague, Czech Republic

[3] Univ York, York YO10 5DD, N Yorkshire, England

[4] Intecs SpA, Rome, Italy

[5] Eindhoven Univ Technol, NL-5600 MB Eindhoven, Netherlands

[6] Open Grp, Brussels, Belgium

[7] AbsInt Angew Informat GmbH, Saarbrucken, Germany

[8] Vienna Univ Technol, Vienna, Austria

[9] GMV, Lisbon, Portugal

来源：

JOURNAL OF SYSTEMS ARCHITECTURE | 2015年 / 61卷 / 09期

关键词：

Real-time systems; Time-predictable computer architecture; PROCESSOR ARCHITECTURE; AETHEREAL NETWORK; CHIP; EXECUTION; CACHE; EFFICIENT; LATENCY; DESIGN;

D O I：

10.1016/j.sysarc.2015.04.002

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Real-time systems need time-predictable platforms to allow static analysis of the worst-case execution time (WCET). Standard multi-core processors are optimized for the average case and are hardly analyzable. Within the T-CREST project we propose novel solutions for time-predictable multi-core architectures that are optimized for the WCET instead of the average-case execution time. The resulting time-predictable resources (processors, interconnect, memory arbiter, and memory controller) and tools (compiler, WCET analysis) are designed to ease WCET analysis and to optimize WCET performance. Compared to other processors the WCET performance is outstanding. The T-CREST platform is evaluated with two industrial use cases. An application from the avionic domain demonstrates that tasks executing on different cores do not interfere with respect to their WCET. A signal processing application from the railway domain shows that the WCET can be reduced for computation-intensive tasks when distributing the tasks on several cores and using the network-on-chip for communication. With three cores the WCET is improved by a factor of 1.8 and with 15 cores by a factor of 5.7. The T-CREST project is the result of a collaborative research and development project executed by eight partners from academia and industry. The European Commission funded T-CREST. (C) 2015 Elsevier B.V. All rights reserved.

引用

页码：449 / 471

页数：23

共 117 条

[1]

Abbaspour Sahar, 2013, P 9 WORKSH SOFTW TEC

[2]

Akesson B., 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), P251

[3]

Akesson B., 2011, Design, Automation Test in Europe Conference Exhibition (DATE), P1

[4]

[Anonymous], INT WORKSH WORST CAS

[5]

[Anonymous], P 10 FPGAWORLD C

[6]

[Anonymous], P 2014 INT C COMP AR

[7]

[Anonymous], 2001, PRINCIPLES ASYNCHRON

[8]

[Anonymous], 2014, OPENACCESS SERIES IN, DOI DOI 10.4230/OASICS

[9]

[Anonymous], SIGBED REV

[10]

[Anonymous], MEM ARCH ORG WORKSH

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